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High Speed Linear Pipeline Multiplier for Signed-Unsigned Number Operating at 20 GHz

Author(s) : Ravindra P Rajput, M N Shanmukh Swamy

Volume & Issue : VOLUME 2 / 2015 , ISSUE 2

Page(s) : 15-24
ISSN (Online): 2394-3858
ISSN (Print) : 2394-3866


Pipeline is the technique in which instructions and arithmetic operations are executed in overlapping. The pipeline consists of a series of processing stages of instruction pipelining or arithmetic pipelining. These processing stages consist of combinational logic circuits, which may be used to generate the partial products, may perform arithmetic or logic operations. All the pipeline stages are separated by the clocked latches. The group of latches is called register and these registers hold the intermediate results between the pipeline stages. The clock signal that latches data into the register is common clock applied to all the registers of pipeline stages simultaneously called the synchronous clock. In general computational operations can be segmented for pipeline operations from two stages and can be extended up to fourteen pipeline stages. For example the processors described in reference [33] the Star-100 vector processor used four stage arithmetic pipeline, eight stage pipeline used in TI-ASC, and fourteen pipeline stages used in CRAY-1supercomputer. The advantages of designing an arithmetic pipeline are to increase throughput, to reduce huge amount of hardware, because the same stages are repeatedly used for the computation. All the RISC (Reduced Instruction Set Computer) systems have the pipeline technique. Modern supercomputers and vector processors require dedicated and high performance multipliers for integer number multiplication of signed and unsigned operands. Since, multiplication hardware is the most time critical, maximum area and power consuming operation, the specialized design of multipliers for least delay, minimum in area and lowest in power consumptions are essential for modern processors. Also in the digital signal processing (DSP) and multimedia applications, the critical delay operations involve many multiplications and addition operations.




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