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High Speed Linear Pipeline Multiplier for Signed-Unsigned Number Operating at 20 GHz

Author(s) : Ravindra P Rajput, M N Shanmukh Swamy

Volume & Issue : VOLUME 2 / 2015 , ISSUE 2

Page(s) : 15-24
ISSN (Online): 2394-3858
ISSN (Print) : 2394-3866

Abstract

Pipeline is the technique in which instructions and arithmetic operations are executed in overlapping. The pipeline consists of a series of processing stages of instruction pipelining or arithmetic pipelining. These processing stages consist of combinational logic circuits, which may be used to generate the partial products, may perform arithmetic or logic operations. All the pipeline stages are separated by the clocked latches. The group of latches is called register and these registers hold the intermediate results between the pipeline stages. The clock signal that latches data into the register is common clock applied to all the registers of pipeline stages simultaneously called the synchronous clock. In general computational operations can be segmented for pipeline operations from two stages and can be extended up to fourteen pipeline stages. For example the processors described in reference [33] the Star-100 vector processor used four stage arithmetic pipeline, eight stage pipeline used in TI-ASC, and fourteen pipeline stages used in CRAY-1supercomputer. The advantages of designing an arithmetic pipeline are to increase throughput, to reduce huge amount of hardware, because the same stages are repeatedly used for the computation. All the RISC (Reduced Instruction Set Computer) systems have the pipeline technique. Modern supercomputers and vector processors require dedicated and high performance multipliers for integer number multiplication of signed and unsigned operands. Since, multiplication hardware is the most time critical, maximum area and power consuming operation, the specialized design of multipliers for least delay, minimum in area and lowest in power consumptions are essential for modern processors. Also in the digital signal processing (DSP) and multimedia applications, the critical delay operations involve many multiplications and addition operations.



Keywords

PPG, MMBE, VCA, SCGP, PPRT, CLCSA, Pipeline, CPA, CSA, RISC

References

  1. Mauro Olivieri “Design of Synchronous and Asynchronous Variable-Latency Pipelined Multipliers” IEEE Transactions on VLSI systems, Vol. 9,  pp. 365-376, April 2001.
  2. Rong Lin, “Reconfigurable Parallel Inner Product Processor Architecures”, Transactions on VLSI systems, Vol. 9, No.2, pp. No. 261-272, April 2001.
  3.  Gregg N. Hoyer, Gin Yee, and Carl Sechen, “Locally Clocked Pipelines and Dynamic Logic”, on VLSI systems, Vol. 10, No.1, pp. No. 58-62, Feb 2001.
  4. Shyh-Jye Jou, Chang-Yu Chen, En-Chung Yang, and Chau Chin Su, “ A Pipelined Multiplier Accumulator Using a High Speed, Low power, Static and Dynamic Full Adder Design, ”, IEEE journal of solid-state circuit, VOL. 32, NO. 1, pp. 114-118,  January 1997.
  5. Lavi A. Lev, Andy Charnas, Marc Tremblay, Alexander R. Dalal, Bruce A. Frederick, Chakra R. Srivatsa, David Greenhill, Dennis L. Wendell, Duy Dinh Pham, Eric Anderson, Hemraj K. Hingarh, Inayat Razzack, James M. Kaku, Ken Shin, Marc E. Levitt, Michael Allen, Philip A. Ferolito, Richard L. Bartolotti, Robert K. Yu, Ronald J . Melanson, Shailesh I. Shah, Sophie Nguyen, Sundari S. Mitra, Vinita Reddy, Vidyasagar Ganesan, and Willem J. de Lange, “ A 64-bit Microprocessor with Multimedia support”, IEEE journal of solid-state circuit, VOL. 30, NO. 11, pp. 1227-1237,  Nov. 1995.
  6. Takahiro Hanyu,  and Michitaka Kameyama, “A 200 MHz Pipelined Multiplier Using 1.5 V-Supply Multiple-valued MOS Current-Mode Circuits with Dual-Rail Source-Coupled Logic”, IEEE journal of solid-state circuit, VOL. 30, NO. 11, pp. 1239-1245,  Nov. 1995.  
  7. Myoung-Cheol Shin, Se-Hyeon Kang, and In-Cheol Park, “An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking”, Department of Electrical Engineering and Computer Science, KAIST, Daejeon, Korea, 2010.
  8. Taesang Cho and Hanho Lee, “A High-Speed Low-Complexity Modified Radix-25 FFT Processor for High Rate WPAN Applications”, IEEE Transactions VLSI systems, Vol. 21, NO. 1, pp.187-191, Jan 2013.
  9. Mehdi Hatamian, A L. Cash, “A 70-MHz 8-bit X 8-bit Parallel Pipelined Multiplier in 2.5-pm CMOS”, IEEE Journal of Solid state circuits,Vol.SC-21, N(). 4, pp.505-513,  Aug 1986.
  10. D A. Henlin, M T. Fertsch, M Mazin, and E T. Lewis, “A 16 Bit W6 Bit Pipelined Multiplier MICROCELL, IEEE Journal of Solid state circuits,Vol.  NO. 2, PP. 542-547, April 1985
  11. W. –C. Yeh and C. –W. Jen, “High Speed Booth encoded Parallel Multiplier Design,” IEEE transactions on computers, vol. 49, no. 7, pp. 692-701, July 2000.
  12. Shiann-Rong Kuang, Jiun-Ping Wang, and Cang-Yuan Guo, “Modified Booth multipliers with a Regular Partial Product Array,” IEEE Transactions on circuits and systems-II, vol 56, No 5, May 2009.
  13. Wang, Shyh-Jye Jou and Chung-Len Lee, “A well-tructured     Modified Booth  Multiplier Design” 978-1-4244-1617-2/08/$25.00 ©2008 IEEE.
  14. G Goto, A Inoue, R Ohe, S Kashiwakura, S Mitarai, T Tsuru, T  Izawa, “A 4.1 ns Compact 54×54-b Multiplier Utilising Sign-Select Booth Encoders”, IEEE journal of solid-state circuit, vol. 32, no. 11, Nov 1997.
  15. C.-H. Chang, J. Gu, and M. Zhang, “Ultra low-voltage low-power CMOS 4–2 and 5–2 compressors for fast arithmetic circuits,” IEEE Trans.Circuits Syst. vol. 51, no. 10, pp. 1985–1997, Oct. 2004.
  16.  Huang and Ercegovac, “High-performance low-power left-to array multiplier design,” IEEE  journal Comput., vol. 54, no. 3, pp. 272–283, Mar. 2005.
  17. Pouya Asadi and Keivan Navi, “A Novel High-Speed 54×54 bit Multiplier” American Journal of Applied Sciences 4 (9): 666-672, 2007.
  18. D Radhakrishnan and A.P Preethy, “Low power CMOS pass logic 4:2 Compressor for High Speed Multiplication”, Roc. 43rd IEEE Mdwest Symp. on Circuits and Systems, p.p 1296-1298, Aug 8-11, 2000.
  19. Do Kim, T Ambler, “Low Power Carry Lookahead Adder by using Dependency between Generation and Propagation”, 2000 IEEE
  20. Radu Zlatanovici, Sean Kao, and Borivoje Nikolic´ “A 240 ps 64 b carry-lookaheadadder in 90 nm CMOS,” IEEE journal of solid-state circuit,, VOL. 44, NO. 2, pp.569-583, February 2009.
  21. Chetana Nagendra, Mary Jane Irwin, Robert Michael Owens, “Area-Time-Power Tradeoffs in Parallel Adders”, ,” IEEE Trans.Circuits Syst. II: Analog and DSP,, VOL. 43, NO. 10, pp.689-702, OCTOBER 1996,
  22. T. P. Kelliher, R. M. Owens, M. J. Irwin, and T.-T. Hwang, “ELM-A Fast Addition Algorithm Discovered by a Program”, IEEE Trans. Comput, VOL. 41, NO. 9, pp.1181-1184, September 1992.
  23. Ahmed M. Shams,Tarek K. Darwish,Magdy A. Bayoumi,”Performance Analysis of Low-Power 1-Bit CMOS full Adder Cells, IEEE Trans.  VLSI Syst, VOL. 10, NO. 1, pp.20-28, FEBRUARY 2002,
  24. Yuke Wang, C. Pai, and Xiaoyu Song,”The Design of Hybrid Carry Lookahead/Carry Select Adders, IEEE Transactions on circuits and systems-II, VOL. 49, NO. 1, JANUARY 2002, pp. 16-24.
  25. S. J. Lee, R. Woo, and H. J. Yoo, “480 ps 64-bit race logic adder,” in Symp. VLSI Circuits Dig. Tech. Papers, pp. 27–28, 2001.
  26. J. Kim, R. Joshi, C.-T. Chuang, K. Roy, “SOI-optimized 64-bit high-speed CMOS adder design,” in Symp. VLSI Circuits, pp. 122–125, 2002.
  27. Amaury Nève, Helmut Schettler, Thomas Ludwig, Denis Flandre,,”Power-Delay Product Minimization in High-Performance 64-bit Carry Select Adders”, IEEE Trans. Very Large Scale Integr. Systems, VOL. 12, NO. 3, pp.235-244, MARCH 2004.
  28. K. Prasad and K. K. Parhi, “Low-power 4-2 and 5-2 compressors,” in Proc. of the 35th Asilomar Conf. on Signals, Systems and Computers, vol. 1, pp. 129–133, 2001.
  29. O. Kwon, K. Nowka, and E. E. Swartzlander, “A 16-bit _ 16-bit MAC design using fast 5:2 compressor,” in Proc. IEEE Int. Conf. Application Specific System, Architectures, Processors, pp. 235–243, 2000.
  30. V Oklobdzija, D Vileger, Simon S. Liu, “A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach”,IEEE transaction on computers, Vol. 45, No. 3, pp. 294-306, March 1996.
  31. C. S. Wallace, “A Suggestion for a Fast Multiplier”, IEEE Transaction on Electronic Computers, pp. 14-17, February 1964.
  32. K. Hwang, Computer Arithmetic: Principles, Architecture, and Design, chapter 3, p. 81. John Wiley & Sons, 1976.
  33. K Hwang and F A Briggs, “Computer Arcitecture and Parallel Processing”, chapter 3 and 4, p.146-156, 170-174, 237-247, McGraw Hill International edition 1985.
  34. Neil H E Weste, David Harris, Ayan Banerjee, “CMOS VLSI Design A circuits and Systems Perspective ” Third edition, Pearson Education, pp.347-349.
  35. Pucknell Douglas A, Eshraghan, Kamran, “Basic VLSI Design,”Third edition 2003, PHI Publication, pp.242-243.
  36. Kai Hwang, F. A Briggs, “Compter Architecture and Parallel Processing”,McGraw Hill International edition-1985,pp.170-176.
  37. Wayne Wolf, “Modern VLSI Design System –on-chip Design”,Pearson Education Asia, Third Edition-2002, Chapter 6.
  38. K.H. Cheng et al., ªThe Improvement of Conditional Sum Adder for Low Power Applications,º Proc. 11th Ann. IEEE Int'l ASIC Conf., pp. 131-134, 1998.